Known in the art is a read amplifier for integrated-circuit storage devices, in which the sources of two amplifier transistors are connected to the first control input, each drain of these transistors being connected to one of two data outputs, each output also having connected thereto the source of one of two load transistors whose drains are connected to the second control input, and the third control input is electrically connected to the gates of the load transistors (Cf. "ELEKTRONIKA" No. 18, 1973, p. 77).
In the known read amplifier the steady state is maintained for some time required to complete the data readout from the entire storage.
In this case, power is continuously drained from the power source through one of the amplifier transistors and one of the load transistors.
Since the power consumed by the read amplifier constitutes a greater part of the whole energy drawn by the storage device, the appreciable portion of that power is lost in the process of readout.
The difference of potentials between the data outputs does not reach the peak value at a steady state of the read amplifier because there is no zero potential across the connection point of one of the data outputs due to the presence of a voltage divider formed by the load and amplifier transistors held in the on state, and the difference of potentials between the connection point of another data output and the drains of the load transistors does not reach the zero level because of threshold losses occurring in these transistors at the steady state of the read amplifier.
This noticeably limits the one-to-zero ratio (difference between the logic one and logic zero values) in entering data into storage elements.
As the read amplifier reaches its steady state, the source potential of one of the load transistors increases, and the potential across its gate does not exceed the potential of the power source because the gates of the load transistors are directly connected to the control input. As a result, there is a decreased difference of potentials between the gate and the source of the load transistor, which slows down the steady-state settling time and shows down the read amplifier speed.